Towards Automated RISC-V Microarchitecture Design with Reinforcement Learning


  • Chen Bai The Chinese University of Hong Kong
  • Jianwang Zhai Beijing University of Posts and Telecommunications
  • Yuzhe Ma The Hong Kong University of Science and Technology (Guangzhou)
  • Bei Yu The Chinese University of Hong Kong
  • Martin D. F. Wong Hong Kong Baptist University



APP: Other Applications, SO: Applications


Microarchitecture determines the implementation of a microprocessor. Designing a microarchitecture to achieve better performance, power, and area (PPA) trade-off has been increasingly difficult. Previous data-driven methodologies hold inappropriate assumptions and lack more tightly coupling with expert knowledge. This paper proposes a novel reinforcement learning-based (RL) solution that addresses these limitations. With the integration of microarchitecture scaling graph, PPA preference space embedding, and proposed lightweight environment in RL, experiments using commercial electronic design automation (EDA) tools show that our method achieves an average PPA trade-off improvement of 16.03% than previous state-of-the-art approaches with 4.07× higher efficiency. The solution qualities outperform human implementations by at most 2.03× in the PPA trade-off.



How to Cite

Bai, C., Zhai, J., Ma, Y., Yu, B., & Wong, M. D. F. (2024). Towards Automated RISC-V Microarchitecture Design with Reinforcement Learning. Proceedings of the AAAI Conference on Artificial Intelligence, 38(1), 12-20.



AAAI Technical Track on Application Domains