Computation Error Analysis of Block Floating Point Arithmetic Oriented Convolution Neural Network Accelerator Design

Authors

  • Zhourui Song Beijing University of Posts and Telecommunications
  • Zhenyu Liu Tsinghua University
  • Dongsheng Wang Tsinghua University

Keywords:

Error Analysis, CNN, CNN Accelerator, FPGA

Abstract

The heavy burdens of computation and off-chip traffic impede deploying the large scale convolution neural network on embedded platforms. As CNN is attributed to the strong endurance to computation errors, employing block floating point (BFP) arithmetics in CNN accelerators could save the hardware cost and data traffics efficiently, while maintaining the classification accuracy. In this paper, we verify the effects of word width definitions in BFP to the CNN performance without retraining. Several typical CNN models, including VGG16, ResNet-18, ResNet-50 and GoogLeNet, were tested in this paper. Experiments revealed that 8-bit mantissa, including sign bit, in BFP representation merely induced less than 0.3% accuracy loss. In addition, we investigate the computational errors in theory and develop the noise-to-signal ratio (NSR) upper bound, which provides the promising guidance for BFP based CNN engine design.

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Published

2018-04-25

How to Cite

Song, Z., Liu, Z., & Wang, D. (2018). Computation Error Analysis of Block Floating Point Arithmetic Oriented Convolution Neural Network Accelerator Design. Proceedings of the AAAI Conference on Artificial Intelligence, 32(1). Retrieved from https://ojs.aaai.org/index.php/AAAI/article/view/11334

Issue

Section

Computational Sustainability and Artificial Intelligence